Poster "electronic design automation" Papers

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Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment

Haoyuan Wu, Haisheng Zheng, Yuan Pu et al.

ICLR 2025arXiv:2502.12732

CORE: Collaborative Optimization with Reinforcement Learning and Evolutionary Algorithm for Floorplanning

Pengyi Li, Shixiong Kai, Jianye Hao et al.

Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism

Ziyang Zheng, Kezhi Li, Zhengyuan Shi et al.

NEURIPS 2025arXiv:2505.21988

MIHC: Multi-View Interpretable Hypergraph Neural Networks with Information Bottleneck for Chip Congestion Prediction

Zeyue Zhang, Heng Ping, Peiyu Zhang et al.

QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation

Yaoyu Zhu, Di Huang, Hanqi Lyu et al.

NEURIPS 2025arXiv:2505.24183

BetterV: Controlled Verilog Generation with Discriminative Guidance

Zehua Pei, Huiling Zhen, Mingxuan Yuan et al.

ICML 2024arXiv:2402.03375

LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits

Chen-Chia Chang, Yikang Shen, Shaoze Fan et al.

ICML 2024arXiv:2407.18269